ASIC design
VLSI design basics
Friday 27 December 2013
Verilog program for half adder
module half_adder(a, b, sum, carry);
input a, b; // default input output inout port declaration is wire datatype
output sum, carry;
assign sum=a^b; // assign = continuous concurrent assignment
assign carry=a&b;
endmodule
No comments:
Post a Comment
Home
Subscribe to:
Post Comments (Atom)
No comments:
Post a Comment